The present invention generally relates to semiconductor devices and more particularly to a high-speed semiconductor device having a dual-layer gate structure and a fabrication process thereof. Further, the present invention relates to fabrication of an air-bridge structure.
A compound semiconductor device having a gate electrode of a refractory metal has an advantageous feature of high operational speed and is used extensively in compound semiconductor integrated circuits for use in ultra-high frequency applications such as a GaAs gate array or a mobile telephony device. A representative example of the mobile telephony device includes portable telephones. Further, such a compound semiconductor device is advantageous in that the diffusion region can be formed relatively easily by a self-alignment process. Further, the feature of using a refractory metal for the gate electrode is advantageous in conducting a thermal diffusion process for forming a diffusion region.
Meanwhile, with the development of telecommunication technology, the analog devices and digital devices used in such ultra-high frequency applications are required to have the feature of higher operational speed and lower power consumption.
The desired increase of the operational speed is most conveniently achieved by reducing the gate length of the compound semiconductor device. On the other hand, such a decrease of gate length invites the problem of increase in the gate resistance as a result of the decrease of the cross-sectional area of the gate electrode associated with the device miniaturization. While it is generally practiced in the art to use a refractory metal silicide such as WSi for the material of the gate electrode in view of high-quality Schottky contact formed between the refractory metal silicide and a compound semiconductor substrate and further in view of the refractory nature of the refractory metal silicide, it is nevertheless desired to reduce the resistivity of the refractory metal silicide gate electrode further. It should be noted that WSi has a relatively large resistivity of about 2.times.10.sup.-4 .OMEGA..multidot.cm. A similar situation holds also in other silicides of refractory elements. Further, in such a high-speed semiconductor device having a reduced gate length, it is desired to employ the so-called LDD structure for suppressing the problem of short channel effect.
In order to reduce the gate resistance, there is a proposal to form the gate structure so as to have an overhang structure. According to this approach, the gate electrode has a dual-layer structure including a Schottky contact layer and a low-resistance layer formed thereon, wherein the lateral size of the low-resistance layer is increased as compared with the lateral size of the Schottky contact layer for minimizing the overall resistance of the gate electrode. The low-resistance layer may be formed for example by forming a layer of a low-resistance metal on the Schottky electrode, typically of WSi, after a thermal annealing process such as a diffusion process to form a diffusion region.
In the case of a compound semiconductor device such as a MESFET in which the diffusion region is formed by a self-alignment process, which uses the gate electrode as a mask, it is necessary to form the foregoing low-resistance layer after the step of forming the diffusion region by an ion implantation process is completed. By forming the low-resistance layer after the thermal annealing process, it becomes possible to use a low-melting metal of low resistance such as Au for the low-resistance layer. On the other hand, such a process has a drawback in that the number of steps for forming the gate structure is increased substantially as compared with the case of forming a conventional single-gate structure.
FIGS. 1A-1I show a conventional fabrication process of a MESFET having a dual-layer gate structure.
Referring to FIG. 1A, there is formed a channel layer 12 on the surface of a semi-insulating GaAs substrate by an ion implantation process of Si.sup.+, and a gate electrode 10 of WSi is formed thereon by a deposition and patterning of a WSi layer. Further, an ion implantation process of Si.sup.+ is conducted into the substrate 18 while using the gate electrode 10 as a mask, to form a diffusion region 14 of the n.sup.- -type.
Next, a side wall oxide film is formed on a side wall of the gate electrode 10 thus formed, and the ion implantation process of Si.sup.+ is conducted again, while using the gate electrode 10 and the side wall oxide film as a mask. By conducting a thermal annealing process on the structure thus obtained, an LDD (lightly doped drain) structure, which is essential for a miniaturized, high-speed MESFET is obtained.
Next, in the step of FIG. 1B, a photoresist layer 20 is applied on the substrate 18 on which the gate electrode 10 is formed as noted already.
Next, in the step of FIG. 1C, the photoresist layer 20 is etched back by a dry etching process or an ashing process such that the top surface of the gate electrode 10 is exposed.
Next, in the step of FIG. 1D, another photoresist layer 22 is formed on the photoresist layer 20 thus etched back by a spin coating process, followed by a patterning process to form an opening 26 in the photoresist layer 22. Further, a metal layer 24 of low-resistance is deposited on the structure thus formed such that the metal layer 24 covers the photoresist layer 22 and the bottom part of the opening 26, which includes the gate electrode 10.
Next, in the step of FIG. 1E, the photoresist layer 20 and the photoresist layer 22 are lifted off together with the metal layer 24 on the photoresist layer 22, and a gate structure carrying the low-resistance metal layer 24 on the gate electrode 10 in the form of an overhang structure is obtained.
Next, in the step of FIG. 1F, an SiN film 28 is deposited on the structure of FIG. 1E as a passivation film, wherein the deposition of the SiN passivation film 28 is conducted by a CVD process such that the passivation film 28 covers a bottom side of the low-resistance overhang structure 24.
Next, in the step of FIG. 1G, a photoresist layer 30 is deposited on the structure of FIG. 1F, followed by a patterning process thereof to form openings 30A and 30B exposing a part of the passivation film 28 covering the substrate 18 on which an ohmic electrode is to be formed. After applying a dry etching process to the exposed part of the passivation film 28 to expose the substrate 18 in correspondence to the openings 30A and 30B, a metal layer 32 making an ohmic contact with the substrate 18 is deposited on the photoresist layer 30 including the exposed part of the substrate 18 by a vacuum evaporation process.
Next, in the step of FIG. 1H, the photoresist pattern 30 thus formed and the metal layer 32 thereon are lifted off, leaving an ohmic electrode on the substrate 18 in correspondence to the foregoing openings 30A and 30B. Hereinafter, the ohmic electrode thus formed will be designated by the reference numeral 32.
Finally, in the step of FIG. 1I, another passivation film 34 is deposited on the structure of FIG. 1H so as to protect the surface of the ohmic electrode 32.
As will be understood from the explanation above, the foregoing conventional process that uses an etch-back process includes a number of steps and the semiconductor device becomes inevitably expensive.
In the fabrication process of FIGS. 1A-1I, there arise also various problems associated with the use of the etch-back process.
One of the problems is the control of the thickness of the photoresist layer 20 after the etch-back process in the step of FIG. 1C. When the etch-back process proceeds excessively after the exposure of the gate electrode 10, the gate electrode itself is etched unwantedly and the thickness or height of the gate electrode 10 may be diminished. When this occurs, the distance between the substrate 18 and the low-resistance layer 24 of the gate electrode structure is decreased, and the stray capacitance of the gate structure increases inevitably. In such a structure in which the distance between the low-resistance layer 24 and the substrate 18 is small, the rate of deposition of the passivation film 28 at the bottom part of the low-resistance layer 24 forming the overhang structure is generally reduced due to the difficulty in the gaseous source materials to be transported into such a small space formed between the substrate surface and the overhang structure of the low-resistance layer 24. As a result of the reduced deposition rate, the passivation film 28 may have a reduced thickness at the bottom side of the low-resistance layer 24. When the thickness of the passivation film 28 is thus reduced, there is a substantial risk that the passivation film 28 does not function as an effective protection layer.
Another problem associated with the fabrication process of the dual-layer gate electrode explained above with reference to FIGS. 1A-1I is that, due to the ionic nature of Ga and As and associated piezoelectricity of the substrate 18 formed of GaAs, the substrate 18, which is under a stressed condition by the gate electrode 10 and the passivation film 28, may accumulate piezoelectric charges underneath the gate electrode 10. The polarity of the piezoelectric charges changes depending on the elongating direction of the gate electrode 10 with respect to the crystal orientation of the GaAs crystal forming the substrate 18. When such piezoelectric charges are induced in the substrate 18 underneath the gate electrode 10, the threshold level of the MESFET is changed accordingly, and it becomes difficult to maintain the threshold voltage of the MESFET uniformly throughout the wafer on which the MESFET is formed together with other similar MESFETs. In such a case, the operational characteristic of the IC chips obtained from a common substrate or wafer, which may be a DCFL (direct-coupled FET logic), variates variously depending on the chip.
Further, the foregoing process of FIGS. 1A-1I relying upon the etch-back process of the photoresist layer 20 suffers from the problem of variation in the thickness of the photoresist layer 20 within the wafer constituting the substrate 18. When this occurs, the thickness of the passivation film 20 underneath the overhang structure formed by the low-resistance layer 24 changes variously and the threshold voltage of the MESFET may vary within the same wafer used for the substrate 18.
It should be noted that such a variation in the thickness of the photoresist layer 20 means that the degree of planarization is degraded in the photoresist layer 20, wherein such a degradation in the planarization is caused as a result of the etch-back process. Generally, it is known that the thickness of a photoresist layer covering a gate structure changes depending on the area of the pattern forming the gate structure. When the pattern of the gate structure has a large area, the photoresist layer covering such a gate structure has a thickness generally the same as the thickness of the photoresist layer formed on a flat surface. When the size of the gate pattern is reduced to the order of submicrons or sub-quarter microns, on the other hand, it is known that the thickness of the photoresist layer tends to become smaller in the part covering the gate electrode pattern than in the part formed on a flat surface. This means that the amount of the etch-back process for exposing the gate electrode 10 of FIG. 1C has to be adjusted depending on the area of the gate electrode patterns that are covered by the photoresist layer 20, while such an adjustment of the etch-back process is difficult.
Further, in the foregoing process of FIGS. 1A-1I, it is desired to cover the structure of FIG. 1A including the gate electrode 10 by a passivation film not shown so as to protect the substrate surface from a damage caused by a dry etching process used in the various steps of the fabrication process of the MESFET. On the other hand, such a passivation film, covering the gate electrode 10, has to be removed after the etch-back process of the photoresist layer 20 by a dry etching process. When there is no sufficient selectivity or difference in the etching rate between the photoresist layer and the passivation film in the foregoing dry etching process of the passivation film, the thickness of the photoresist layer is reduced inevitably as a result of the dry etching process conducted so as to remove the passivation film from the top surface of the gate electrode 10. When there exists such a difference in the etching rate, it becomes difficult to control the dry etching process. Because of this, the process of FIGS. 1A-1I has suffered from the problem of limited degree of freedom in setting the process condition.
Further, there is a proposal to form the T-shaped gate electrode to have a dual-layer structure without using the etch-back process as disclosed in the Japanese Laid-Open Patent Publication 01-184958.
According to the process of this prior art, a resist layer having a dual-layer structure is provided on a substrate after the step of forming a Schottky gate electrode on the substrate such that the dual-layer resist covers the Schottky gate electrode. The dual-layer resist includes a first layer of high sensitivity and a second layer of low sensitivity formed on the first layer, and the dual-layer resist thus formed is subjected to a controlled exposure process while using a photomask formed with a mask window smaller in size than the size or length of the Schottky gate electrode. As a result of a development process that follows the exposure process, the dual-layer resist is dissolved until the top part of the gate electrode is exposed, wherein it should be noted that the first layer resist having a higher sensitivity dissolves faster in the lateral direction in the development process in the exposed part as compared with the second layer resist, resulting in an inversely tapered cross-sectional structure for the resist opening formed in the dual-layer resist. Such a resist opening, characterized by the size which is larger in the central part than in the top part, is advantageous for conducting a lift-off process of the resist by using an organic solvent.
In the foregoing prior art, it should be noted that the exposure dose and the developing time are controlled carefully such that the resist opening thus formed has a reduced lateral size in the bottom part thereof corresponding to the lower photoresist layer, such that the resist opening exposes only the top part of the gate electrode. More specifically, the exposure dose has to be controlled such that the bottom part of the lower photoresist layer of high sensitivity is not substantially exposed. Further, the development process has to be controlled such that the bottom part of the lower photoresist layer, in which the Schottky gate electrode is embedded, is not dissolved.
After the development process of the foregoing dual-layer resist to form the resist opening, a low-resistance metal such as Au is deposited on the Schottky gate electrode by an evaporation deposition process, to form the desired T-shaped dual-layer gate structure including the Schottky gate electrode and a low-resistance layer formed thereon. After the formation of the dual-layer gate structure, the dual-layer resist is lifted off together with the low-resistance metal deposited thereon, leaving behind the T-shaped dual-layer gate structure on the substrate.
In the foregoing prior art process of the Japanese Laid-Open Patent Publication 01-184958, it is necessary to use a photomask having a window with a width narrower than the size of the lower electrode that defines the gate length of the device for the exposure process, while it should be noted that the approach of using such a photomask cannot reduce the size of the resist opening in conformity with the gate electrode of the reduced gate length. As noted previously, the lower photoresist layer has a high sensitivity and is exposed by a very small amount of incident optical beam. Thereby, the lower photoresist layer is dissolved rapidly at the time of the development process, and thus, there appears a tendency that the substrate surface is exposed at both sides of the gate electrode of the minute gate length. In fact, it is necessary to use a zero width for the mask window in order to form the gate electrode with a gate length of 0.2 .mu.m, while the use of such a photomask having a zero-width window is unrealistic. Even if a mask window of 0.15 .mu.m or less can be formed successfully in the photomask by a high-resolution exposure process such as an electron beam exposure process, the resist structure thus formed has a very minute resist opening in the upper photoresist layer, and the formation of the desired T-shaped gate structure through such a resist structure becomes difficult.
Meanwhile, a GaAs analog integrated circuit is generally formed to construct a so-called MMIC (microwave monolithic integrated circuit), in which active devices such as FET are integrated on a common substrate together with conduction strips, diodes, resistors, capacitors and inductances, for facilitating operation at a microwave band. In order to increase the operational frequency of such an MMIC further, it is necessary to minimize the stay capacitance associated with the conduction strips.
In order to minimize the stray capacitance of a conduction strip, there is a proposal to form an air bridge structure in which the conduction strip extends over the substrate with a separation therefrom by a space or void. In such an air bridge structure, in which an insulation film, which is otherwise provided between the conduction strip and the substrate, is replaced by an air having a minimum dielectric constant, the stray capacitance associated with a conductor strip is minimized and the high frequency operation of the integrated circuit is facilitated.
FIGS. 2A-2I show a conventional process of forming an air bridge structure.
Referring to FIG. 2A, a resist pattern not illustrated is formed on a substrate, followed by a lift-off process, to form a lower electrode 38.
Next, in the step of FIG. 2B, a photoresist layer is applied on the structure of FIG. 2A, followed by a patterning process, to form a photoresist pattern 40 having openings 41.
Next, in the step of FIG. 2C, an exposure process is conducted on the photoresist pattern 40 by a ultraviolet irradiation, followed a thermal annealing process to induce a curing in the photoresist pattern 40, and a step of FIG. 2D is conducted in which a metal layer 42 is deposited on the resist pattern 40 thus cured in the step of FIG. 2C by a sputtering process. As a result of the annealing process conducted in the step of FIG. 2C, the photoresist pattern 40 is deformed to have an arcuate curved surface.
Next, in the step of FIG. 2E, a photoresist pattern 44 is provided on the structure of FIG. 2D with a resist window such that the resist window exposes a part of the metal layer 42 in which an air bridge structure is to be formed. Further, an electroplating process is conducted in FIG. 2F in which a thick wiring pattern layer 46 is formed on the metal layer 42 in correspondence to the resist window exposing the metal layer 42, while using the metal layer 42 as an electrode.
Next, in the step of FIG. 2G, the resist pattern 44 is removed by an ashing process, and the part of the metal layer 42 not covered by the thick wiring pattern layer 46 is removed by an ion milling process. Further, the resist pattern 40 remaining under the thick wiring pattern layer 46 is dissolved in the step of FIG. 2I, and the desired air bridge structure is obtained by the remaining wiring pattern layer 46.
There is also a proposal in the Japanese Laid-Open Patent Publication 3-126247 to form an air bridge structure by a more simple process. According to this simplified process, a lower wiring layer is formed on a substrate, and a pillar structure is formed on the lower wiring layer thus formed so as to support an upper wiring layer. Further, a photoresist layer is provided so as to cover the lower wiring layer and the pillar structure and a groove is formed in the photoresist layer by an image reversal process such that the upper part of the pillar structure is exposed. Further, a metal layer having a width smaller than the depth of the foregoing groove is deposited on the structure thus formed, followed by a lift-off process to form a wiring pattern. Simultaneously to the lift-off of the resist layer, there is formed a space underneath the wiring pattern and the desired air bridge structure is obtained.
In the conventional fabrication process of the air bridge structure of FIGS. 2A-2I, there arises a problem, when depositing the metal layer 42 on the cured photoresist pattern in the step of FIG. 2D as the electrode layer of the electroplating process, in that the deposition of the metal layer 42 may induce a formation of winkles in the cured photoresist pattern 40. It should be noted that the optimum condition of the thermal annealing process for curing a photoresist changes slightly depending on the nature of the photoresist. In the case the curing of the resist pattern 40 is not sufficient, there is a substantial risk that the deposition of the metal layer 42 induces a winkle formation in the resist pattern 40 as a result of the stress caused by the deposited film. When such a winkle is caused, the air bridge structure may be deformed. On the other hand, excessive curing of the resist pattern 40 tends to cause an incomplete removal in the last step of FIG. 2I. The process window for curing the resist pattern 40 is thus substantially limited.
Another problem associated with the foregoing process of FIGS. 2A-2I is that the photoresist pattern 40, thus changed the shape to have the arcuate structure, may have an insufficient mechanical strength for supporting the air bridge structure. In this case, the air bridge structure formed on the photoresist pattern 40 undergoes a deformation, and the conductor strip may not perform as desired or as designed.
Further, the foregoing process of FIGS. 2A-2I includes a large number of steps not preferable in view of reducing the cost of the semiconductor device.